- Cite This Article as
- Corresponding Author
The paper describes a 6bit, 1Msps Pipeline Analog to Digital Converter implemented in 0.6?m CMOS technology. The design operates at ±5V dc supply. Circuit techniques used include a precise comparator, operational amplifier which works on 1.5bits per stage and non-overlapping clock. A switched capacitor is used to sample and multiply at each stage.
[Manjuvani.K.M, Manasa k chigateri, Manjunath K M and Sharan basavaraj B. (2016); DESIGN OF HIGH SPEED,6-BIT PIPELINE ADC WITH BUILT-IN DIGITAL ERROR CORRECTION UNIT USING SUBMICRON CMOS TECHNOLOGY. Int. J. of Adv. Res. 4 (6). 519-524] (ISSN 2320-5407). www.journalijar.com
Article DOI: 10.21474/IJAR01/792 DOI URL: http://dx.doi.org/10.21474/IJAR01/792
Share this article
This work is licensed under a Creative Commons Attribution 4.0 International License.