13May 2018

DESIGN AND IMPLEMENTATION OF NOVEL NOC ARCHITECTURE ON FPGA.

  • Research Scholar, Jain University, Bangalore, India.
  • Professor, ECE Department , SJBIT, Bangalore, India.
  • Head of department, ECE, SJBIT Bangalore India.
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A 2-Dimensional mesh has low design complexities and very good match to the rectangular processor architecture which makes them the favorite Network-on-Chip (NoC) topology that is most used more often for on-chip communication of processor with multi-core arrays. However, it has some of the basic problems such as local traffic congestion which may arise due to various levels of traffic with other neighbor cores this is a major problem as it increases high latency and huge power consumption for the chip. To overcome the above stated problems, we propose a novel architecture of 6-neighbor hexagonal mesh topology for implementing on an FPGA. The design is developed using verilog hdl language and tested on modelsim for the functional correctness. The architecture developed has also been tested to overcome some of the basic networking problems such as deadlock and livelocks. It is also implemented and tested on latest Xilinx FPGA such as Vertix 6 and Atrix 7 for the physical implementation. The grid topology with 6-neighbor hexagonal pattern is implemented and has a very less area on chip in comparison with the 4-neighbor 2D mesh, it also has much more effective interconnect with the inter-processor that results in an area reduction of 21%, an average power reduction of 17%, and a communication distance among inter processor on an average is decreased by 19% This makes the design more effective as compared to traditional 2D architecture.


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[Shilpa K Gowda, Rekha K R and Nataraj K R. (2018); DESIGN AND IMPLEMENTATION OF NOVEL NOC ARCHITECTURE ON FPGA. Int. J. of Adv. Res. 6 (5). 1-9] (ISSN 2320-5407). www.journalijar.com


Shilpa K Gowda
Jain University

DOI:


Article DOI: 10.21474/IJAR01/7003       DOI URL: http://dx.doi.org/10.21474/IJAR01/7003


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