AN IN-SITU TIMING-ERROR PREDICTION AND PREVENTION TECHNIQUE FOR VARIATION-TOLERANT MAC-UNIT.

achieved with CANARY based adaptive DVS as compared to classical DVS technique over the wide spectrum of functional frequency range. The SPICE platform is used for the detailed analysis and step by step implementation of CANARY based DVS technique.

In this paper, a CANARY based Dynamic Voltage Scaling (DVS) technique is applied on a 17-bit Multiplier Accumulator (MAC) Unit in 0.55-nm technology to critically analyze the voltage safety margins and energy efficiency during the worst case of Process, Voltage and Temperature (PVT) conditions. The CANARY based DVS technique incorporates an inherent in situ error prediction feature, with a mechanism to prevent the errors to impact the Design under Test (DUT). In CANARY based DVS technique, the supply voltage is reduced automatically. Error prediction and prevention mechanism ensures correct operation and lesser voltage supply. Supply voltage is intentionally scaled down till the first failure point of MAC unit to reach at an optimal tradeoff [17] between voltage supply and energy consumption. It is observed from the simulation results that the energy savings up to 38.5% is achieved with CANARY based adaptive DVS as compared to classical DVS technique over the wide spectrum of functional frequency range. The SPICE platform is used for the detailed analysis and step by step implementation of CANARY based DVS technique.

…………………………………………………………………………………………………….... Introduction:-
In deep submicron Integrated Circuits (IC) technologies, process-induced parameter variations cause performance fluctuations, which is an important challenge to be addressed. Due to this, the traditional worst-case methodology of design is no more effective as process variations require more design margins. To deal with this problem, the prediction of parameter variations can play a vital role in manufacturability of silicon devices [1,2,3]. Lower technology nodes are setting a trend of lowering supply-voltage and tremendous increase in clock frequency. These changes of voltage and temperature variations make the design more and more tedious. To achieve a robust design along with above discussed constraints, designers are focusing on Design for Manufacturability (DFM), which is a key to solve these serious problems. As the worst cases rarely occur, so it is always better for the designers to focus on typical cases, called as typical-case design methodology. In recent time, different typical-case design methodologies are proposed, such as Razor circuit [4][5], Canary circuit [12], approximation-circuits [6], Algorithmic Noise Tolerance (ANT) [9], Constructive Timing Violation (CTV) [7], TEA time [10] etc. This paper, focuses on the Canary based DVS technique to critically analyze the voltage safety margins and energy efficiency during, worst case PVT conditions.

ISSN: 2320-5407
Int. J. Adv. Res. 5(7), 1772-1781 1773 As out of these techniques some compromises with throughput of the system like approximation, CTV, some techniques like ANT is highly dependent on EDA. Techniques like Razor and CANARY are error correction and detection based where Razor technique results in circuit overhead for re-execution. So we have adopted here the Canary technique just to focus on power reduction without any overhead or compromise in throughput.
Explosive, exceptional and exhilarating kind of growth is observed in semiconductor and computational operations, which is carried out by Digital Signal Processing (DSP). In a DSP, the computational operations are threaded through some mathematical algorithms of different forms. These operations are processed with the help of different kind of normal or application specific MAC units. The Block diagram of a classical DSP is presented [13] in Fig. 1.
Being a main stream unit of processing, the MAC unit performs, most of the time, at maximum throughput as per amount of data processed per unit time. Moreover, in handy systems, the MAC units are expected to consume high power and as a result of it the MAC unit governs the speed and power of the system. The most efficient MAC utilization in terms of power and speed depends upon the technology chosen, its characterization, architecture type, its fundamental blocks and primitive cell realization.
In this paper, a CANARY based DVS technique is applied on a 17-bit Multiplier Accumulator (MAC) unit in 0.55nm technology to critically analyze the voltage safety margins [8] and energy efficiency during, worst case PVT conditions. The performance of CANARY based DVS technique is also compared with classical design technique over the wide spectrum of frequency range. The comparative analysis is based on some constant supply-voltage versus adaptively varying supply-voltage to enhance the speed and performance whenever required. This study will help researchers to adopt some new technologies and techniques, while designing a suitable MAC block for any Application Specific Integrated Circuit (ASIC) in signal processing applications.
The Mac Unit:-Generally, the architecture of a MAC unit is classified as parallel [14], recursive [15] and shared segmented structure. The architecture named as recursive, is based on "divide and conquer" methodology. Larger data is divided into smaller ones to be processed by individual units. In MAC unit, the multiply-accumulation is an iterative calculation process performed by smaller units through several cycles. The number of multipliers and adders called recursively are responsible for latency and throughput of the complete MAC unit. Ideally, the MAC unit operation can be understood in four phases like: Data to be processed, fetched from internal memory  Multiplication is performed  Summation is performed 1774  Performed A.B + Acc, stored in the internal memory.
Hence, the function of MAC unit can be understood well from the arithmetic relation mentioned in equation (1): (1) Where A, B are the multiplicand and multiplier respectively. The "n" is the numbers of pairs to be multiplied and accumulated. Fig. 2 shows a typical MAC architecture in detail. There are two inputs, multiplicand and multiplier of some bit widths. The width of the MAC final output is defined by the width of (2) and (3) and also presented in Fig. 2. This extra bit for "Z" is always needed and is named as Guard Bits, also named as Extension Bits, which is essentially required for more robust design. Being a main stream and most critical unit of processing, the MAC unit is adopted as the most suitable module to analyze and study the effectiveness of the adaptive supply-voltage system.  Table  1.

Fig. 3:-MAC Unit Pin Diagram
Three Guard / Extension Bits are kept to avoid overflow of the MAC output as presented in equation (4):

MAC UNIT Nreset Clock
In this work the MAC unity is designed and developed in Verilog RTL and the functionality of RTL and synthesized netlist is verified through simulations. In the next sections of the paper, the development, integration and analysis of the system are given in details. It also shares the variation of results in terms of power efficiency and functional range of MAC unit, w.r.t., the system without DVS sub-system.

The CANARY Integration:-
To getridof the worst case margin, the Flip-Flops of MAC are paired with CANARY Flip-Flop [12,16] as per shown inFig.4. Input of the CANARY Flip-Flop is delayed little more with a delay cell. Output of Main Flip-Flop and of respective CANARY flip-flop which is compared through XOR gate as comparator logic, output of XOR gate is named as WARN or Error Signal. This is connected to the Monitor and Voltage Control unit as an input. There are different type of errors [11] presented from time to time but this is hardware generated comparative error.

Adaptive DVS System Architecture:-
The CANARY integrated MAC unit is integrated in In-Situ Adaptive DVS sub-system as presented in Fig. 5 with the help of block diagram [4,18]. Different supply-voltages are applied to the active supply-voltage block which acts as per the instruction of Units "Supply Select & Timer" and "Monitor and Voltage Control", respectively. Unit Monitor and Voltage Control reacts as per the output WARN/Error, of CANARY comparator unit. The complete sub-system [18] as shown in Fig.5 is a kind of closed loop feedback system, where the system reacts on the error prediction mechanism of CANARY module and completes the loop by adjusting the supply-voltage adaptively. As per the block diagram, it is clear that "Supply Select & Timer" and "Monitor and Voltage Control" units play a vital role in the complete sub-system. In the upcoming sections, these units are described in detail.

Monitor and Voltage Control Unit:-
The "Monitor and Voltage Control" unit decides about stepping up/down the supply-voltage adaptively, to avoid any assertion of Error/WARN signal by CANARY cell. This unit is realized with the help of state machine, where numbers of states are directly proportional to the number of quantized supply-voltages. In this work we have quantized the supply-voltage in eight levels with constant difference of 100mV.  Fig. 6 and are also depicted in Table 2 in detail.

Fig. 6:-State Machine of Monitor and Voltage Control Unit
On releasing the reset of the system, this unit starts with State7 with highest voltage level and adaptively resumes the consecutive state as per the WARN / Error signal activated by CANARY module. Once there is no WARN / Error signal asserted, this unit adaptively switches to the lower state to step down the supply-voltage. On the other side, if there is any WARN / Error signal asserted by CANARY module, system resumes the next respective state to step-up the supply-voltage. As it is the most critical part of the sub-system, this unit is always connected to the highest available voltage level.

Volt
The Supply Unit:-There are eight different voltage supplies starting from 2.6 Volt till 3.3Volt. Practically, we need an accurate voltage regulator to supply this kinds of supply-voltage, but this is beyond the scope of this study, so we have used here the digitalized version of voltage regulator, implemented by pass gates switches, as shown in Fig. 7.

Fig. 6:-Supply Unit
Signals Active_Supply 0 , Active_Supply 1 ……… Active_Supply 7 are controlled by Monitor and Voltage Control unit through its respective states and accordingly that supply-voltage will be available at Pin V DD .  The Sub-System Integration:-The MAC unit Verilog netlist with CANARY flip-flop paired at each MAC unit critical path capture side Flip-Flop is created. Monitor and Voltage Control unit Verilog netlist is integrated with MAC unit netlist and the integrated netlist is streamed in Virtuoso to get the transistor level SPICE netlist. The other units like supply voltages unit and all are also integrated to the schematic and a complete sub-system are integrated as per schematic shown in Fig. 8.   Fig 8:-Adaptive DVS Architecture

The System And Simulation Statistics:-
The complete MAC Unit statistics and simulation scenarios are summarized in Table 3 and 5, respectively. The light corners are chosen for MAC unit without the CANARY technique but the complete adaptive system with CANARY technique is simulated over the complete range of Supply-Voltage and Temperature mentioned in Table 5.

Spice Simulation Results:-
In this section of the paper the simulation results of the MAC unit without adaptive technique and afterwards the simulation results of the MAC unit with adaptive technique are discussed. The Functional Range of MAC unit at different voltage and temperature is presented with the help of Shmoo-Plot as depicted in Table 5 and 6. It is observed from the results that the MAC unit is behaving correctly in range of BC Freq Limit = 500 MHz and WC Freq Limit =312 MHz  The system power is evaluated over the wide spectrum of frequency at each temperature and fixed supply voltage range as shown in Fig.9. In Fig.9

MAC Unit with Adaptive Technique Results:-
The MAC unit with CANARY based adaptive technique is simulated at a wide range of frequency at different temperature ranges as per the Table 4. The simulation results are presented in this section in detail:

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As per the CANARY based adaptive technique, CANARY flip-flop setup time is violated before main flip-flop by an defined time depending upon delay unit. On failure of CANARY flip-flop WARN / Error signal is asserted. Numbers of WARN / Errors signals asserted by different CANARY cell at different temperature and average supply-voltage w.r.t. different frequencies and respective temperature are presented in Fig.10 and 11, respectively. Each time there is mismatch between the main Flip-Flop and the CANARY Flip-Flop, the system adaptively switches to next level of supply-voltage and vice versa. Hence, the supply-voltage applied at the system is different at a different time frame. The average voltage applied for a fixed (1000ns) simulation period can be understood from Fig. 10. If there is no error, the supply-voltage is reduced to lower level and frequency is increased in next simulation. Subsequently, after a certain limit, the further increase in frequency require an increase in supplyvoltage. As per the Fig 10, there is increase in number of CANARY mismatches with increase once frequencyincrease cross some threshold which is different at different temperature. As per Fig 11, for lower range of frequencies average supply-voltage reduces as adaptive system able to drag down the supply-voltage and then for middle range of frequency it gradually increases. For further frequencies the system is only able to sustain at highest supply-voltage.

Result Analysis:-Power Consumption Comparison:-
It is observed from the SPICE simulation results that the active supply-voltage will be at some lower level as compared to the worst case simulations at different fixed supply voltage initially till the CANARY module starts giving warning signals and then gradually increases at higher frequencies and graph follows the highest supplyvoltage (3.3 Volt). As a result of it, the power consumption should also follow the same trend. The power consumption of the MAC unit with and without adaptive technique is shown in Fig.12.  It is observed from the simulation results that up to a certain frequency at each temperature, the power consumption is lower and then starts increasing with CANARY based DVS technique. As soon as the system starts getting CANARY warning, it increases the supply-voltage. As a result of it the power consumption gets increased and finally matches with it at the highest supply voltage power consumption.
Power Gain:-It is observed in section 6.1 that the initial power consumption is maintained at lowest possible level, then it gradually increases and reaches finally up to the level of power consumed at highest voltage i.e 3.3Volt. In this section the percentage power gain w.r.t fixed supply-voltage systems, at a wide spectrum of functional frequency at different temperatures are shown in Fig. 13 with CANARY based DVS technique. It is observed from Fig. 13 that at each temperature initially the power gain is increased, up to the some respective frequency and then decreases. This behavior is observed because of the adaptive change of supply-voltage as discussed in earlier session 6.1.

Conclusions:-
In this paper, we presented an accurate methodology for predicting the required supply-voltage to optimize the power consumption of the system. The required value of a system voltage is exploited in an adaptive fault-tolerant manner in design. Different scaling-up and scaling-down mechanism is developed and verified for the effectiveness of the power saving. The detailed gain in power consumption at various temperatures and supply voltages are depicted in Table 7 without compromising the system functional bandwidth and throughput.  Table 7, the maximum gain is 28.5%, which is observed over the simulation period of only 1000ns. As the system will operate for more prolonged time the gain will be more as a device will sustain for a longer time at optimum or minimum possible voltage level.
As compared to Classical worst-case margin methodology, here we did not exclude any margin while considering the system without Adaptive Technique. So, if we consider a 10% to be the impact of extra margin the overall gain of the Adaptive Technique will be 28.5+10=38.5% which will increase as the duration of usage is increased.