AN EFFICIENT DESIGN OF DIGITAL DOWN CONVERTER FOR SOFTWARE DEFINED RADIO APPLICATION

Adaptive wave pipelining is the methodology used for improving the overall performance of Software Defined Radio (SDR). This method is a functional combination of wave pipelining and hybrid technique. Wave pipelining is the methodology used for improving the performance without using the intermediate latches, at the same time it performs the same operation as pipelining. Hybrid technique is the mechanism that is used for introducing registers for achieving the timing constrain. This technique is implemented in the Direct Digital Synthesizer (DDS) which is the integral part of a Digital Down Converter (DDC) in the Digital Front End (DFE)/ Intermediate Frequency (IF) of Software Defined Radio (SDR). This paper presents the principles of wave pipelining and the method for executing the computer algorithm named Coordinate Digital Rotation Digital Computer (CORDIC) using wave pipelining. Xilinx

Adaptive wave pipelining is the methodology used for improving the overall performance of Software Defined Radio (SDR). This method is a functional combination of wave pipelining and hybrid technique. Wave pipelining is the methodology used for improving the performance without using the intermediate latches, at the same time it performs the same operation as pipelining. Hybrid technique is the mechanism that is used for introducing registers for achieving the timing constrain. This technique is implemented in the Direct Digital Synthesizer (DDS) which is the integral part of a Digital Down Converter (DDC) in the Digital Front End (DFE)/ Intermediate Frequency (IF) of Software Defined Radio (SDR). This paper presents the principles of wave pipelining and the method for executing the computer algorithm named Coordinate Digital Rotation Digital Computer (CORDIC) using wave pipelining. Xilinx ISE 14.75 design suite is used as the software for simulation of the proposed system. Copy Right, IJAR, 2017,. All rights reserved.

…………………………………………………………………………………………………….... Introduction:-
A SDR is defined as the functional system that is implemented in software and whose physical layer behavior can be changed by changing the software function. In SDR waveform signal processing is done digitally. The SDR was developed to obtain transmission link inside different bands of spectrum with a single device. SDR is a radio that solves the gap between different Link-layer protocols and provide an ideal solution for the different functional and performance problem by building a generic platform that switches the functionalities using software control. Fig. 1 shows the basic architecture of SDR. Fig. 2 shows SDR modules in the two-axis graph Processing Intensity vs. Flexibility that determines some of spectrum signal processing associated with SDR system [1]. The upper left area indicates dedicated functions like ADC & DDC that functions with hardware. Flexibility defines the range of ease to complete the function. The lower area determines the functions like analysis and decision making which are functional parameters.    DDC is a complex mixer that shifts the frequency of particular range to baseband frequency. The functionality of DDC is mixing and multiplying the retrieved samples with the available digitized stream of data that produces corresponding sine and cosine phase and quadrature channels. DDC's decimate to a lower sampling frequency rate by using different stages of decimation filters. Filtering is performed to limit the bandwidth with the help of linear phase filters. The signals with low data rates are easy to be processed on a low speed functional DSP processor.

DDS/NCO:-
Direct Digital Synthesizer (DDS) is also termed Numerically Controlled Oscillator (NCO). When brought together with a DAC to create an analog output waveform, the system is called a (DDS).
NCO is digital signal generators that generate synchronous, discrete time, discrete value representation of a waveform. In NCO, digital accumulator is used to generate the address into a lookup table. Fig. 4 shows the NCO/DDS functional block diagram.
The system is common, both in hardware and in software. It allows instantaneous changes in the instantaneous frequency or phase of the generated waveform, while maintaining a continuous phase property in the output.

Theory of cordic algorithm:-
Jack. E. Volder in 1959 coined the Coordinate rotation digital computer (CORDIC). The methodology is applicable for functional execution of digital communication system. It has the characteristics of reading and analyzing the values of any functions that include trigonometric, hyperbolic, arithmetic, vector rotation, and logarithmic [3]. It computes the rotation of vectors by addition and shift operation. They are executed either in rotation mode or vectoring mode [4]. Table 1 shows the output for each mode of operation in different coordinate system. There are three different systems in which the CORDIC can be operated and they are circular coordinate system or in linear coordinate system or in hyperbolic coordinate system.
Denotes direction of rotation that can have value of 1 or -1. This is determined by the rotational direction whether positive rotation or a negative rotation. K i Denotes scaling factor of ith iteration that can be computed at the end stage as it is determined by combination of all stages.
The K value is given theoretical as K = π i * K i = .60725 Table 1:-Output for each mode of operation in different coordinate system Pipeline CORDIC:-The entire existing system is designed based on pipeline CORDIC. In the pipelined CORDIC architecture, each module is responsible for each elementary rotation occurring in the different modules selected [8] [9]. The modules are combined through immediate latches as shown in Fig. 6. Every stage of CORDIC includes addition, subtraction and shifting operation.    Table 2 shows the pre computed values of the angle α i needed for the i th iteration that will be stored in ROM memory location. Overflow is parameter that occurs whenever a rotational angle crosses from a positive right angle to negative one [5] [9]. To avoid this there is a functional overflow system control is added. This analyses the nature of operand involved in the operation. If an overflow occurs it retains its previous value. Proposed system:-

Advantages of CORDIC Pipeline Over
The proposed system is to design further better architecture that can improve the overall performance of SDR in its applications. There by through comparative and analytical study Adaptive Wave Pipelining (AWP) is the technique that can further improve overall performance of SDR in all aspects comparative of area, speed, throughput, delay.
Adaptive wave pipelining (AWP) is the technique that is implemented in the proposed system. It is combinational logic of wave pipelining and hybrid technique. Wave pipelining is the methodology which is similar to pipelining with the difference that intermediate registers are not used for the wave pipelining execution.
Wave pipelining is an alternative pipelining technique that reduces the clock loads, area, power and latency at the same it retains the external functionality and timing of the circuit [12] [13]. Wave pipelining was coined by Cotton [8] and initially named it as maximum rate pipelining. Synchronization of signals in wave pipelining is achieved by manipulating the timing of signals due to lack of intermediate registers. Fig. 8 represents the block diagram of wave pipelining. Since there is manipulation of the signals on a periodic basis registers are introduce for the clocking function. This method of introducing the registers in wave pipelining leads to the design of proposed system AWP.
Timing Function:-Timing requirements for a wave pipeline circuit is done by attaching the registers at the input and output at the periodic basis [14]. The clocking function is derived using certain parameters that help in deriving the timing constrain for the clocking function. The timing function is illustrated through the following formulas:-T max > D max + T set + S clk T cpture < T clk + D min − (T hold + S clk ) T clk > D max − D min + (T set + T hold + S clk ) Where:-D max -Is difference between longest path D min −Is the difference between shortest path T set − Set time T clk − Clock time T hold − Hold time S clk − Clock skew      Table 3 shows the theoretical comparison of the existing and proposed system using CORDIC through the literature survey.
Outputs obtained for the CORDIC with AWP using Xilinx synthesis.
KIT USED: -Artix 7 DEVICE:-XC7A100T PACKAGE: -FTG256 SPEED: --3 Fig. 11:-And Fig. 12. Represent the output wave for AWP for the specified inputs. They are analyzed through the case studies. Inference from the above wave forms fetched is that, whenever each time the value for inputs is forced in the ISim simulator there is corresponding change in the outputs of the wave. The number of register values is clearly available from the output window for further clarification synthesis reports are taken and compared. Fig. 14. And Fig. 15. Is the utilization summary report that determines the number of registers and LUT's used along with which the delay and maximum frequency, is specified from the synthesis report. These utilization summary of both CORDIC pipeline and AWP are used for comparison.  Graph representations are made for comparison and displaying the comparative area, delay and frequency (throughput). Table 4 shows the practical comparison of the both systems using the physical values fetched after running the codes in Xilinx ISE 14.75 design suite. Fig. 16,17,18,19 are the graph representation done from the synthesis report and utilization summary.

Fig. 16:-Graph representation of area utilization
Inference: From the above graph it is clear to knowledge that the number of slices used by AWP is lesser than the number of slices used by CORDIC pipeline. Hence the area occupied by AWP is less compared to other method.  Inference: the above graph is plotted between number of slice LUT's used vs delay. From the previous graph representation it is clear that CORDIC pipeline uses more LUT's than AWP. Hence the delay acquired for CORDIC pipeline is more than the proposed system that is AWP. Fig. 19:-Power response.
Inference: the above graph is plotted between number of registers used vs power. Since the number of registers used is less in AWP the power consumed in this method is less. This is been analyzed by plotting the graph

Conclusion:-
The entire proposed system is designed and executed using Xilinx. The function is designed in such a manner the end users can modify them according their requirements and application. Since FPGA is chosen as target technology the design has resulted in consumption of low area, power with increased speed and throughput.
The entire project work is focused on designing of efficient DDS to improve the efficiency of DDC and improve the overall performance of SDR. In future the entire DDC structure can be designed with the developed AWP technique and better efficient SDR structure can be evolved.