TUNABLE MIXED DECIMATION MULTIPATH DELAY FEEDBACK FOR RADIX 2

The Decimation Multipath Delay Feedback (M 2 DF) is a technique for the radix 2 k FFT, which eliminates the stand by time of arithmetic modules in computing units. In this paper tunable M 2 DF architecture is proposed. In this, tunable arithmetic units are utilized in place of conventional arithmetic units to overcome the under utilization of arithmetic units in conventional M 2 DF architecture. The results show that, the tunable M 2 DF technique utilizes the lesser number of LUTs and slice registers than the conventional M 2 DF technique. In addition, the proposed technique having advantage of high throughput with reduced delay and area compared with conventional M 2 DF.

The Decimation Multipath Delay Feedback (M 2 DF) is a technique for the radix 2 k FFT, which eliminates the stand by time of arithmetic modules in computing units. In this paper tunable M 2 DF architecture is proposed. In this, tunable arithmetic units are utilized in place of conventional arithmetic units to overcome the under utilization of arithmetic units in conventional M 2 DF architecture. The results show that, the tunable M 2 DF technique utilizes the lesser number of LUTs and slice registers than the conventional M 2 DF technique. In addition, the proposed technique having advantage of high throughput with reduced delay and area compared with conventional M 2 DF.

Introduction:-
Fast Fourier Transform (FFT) is mostly used algorithm for Discrete Fourier Transform computation in the field of signal processing. The area efficient and high performance FFT implementation throws a challenge on the designers. Hardware designers are putting effort to design effectual architectures for the computation of the FFT to meet required specificatons and real-time fulfillment of present applications. Various techniques have proposed over the years to tradeoff the area and performance of the FFT. Pipelined architectures [1] are extensively used because they will achieve more throughputs and small latencies relevant for today's applications to achieve small area and to dissipate less power. The single path delay commutator (SDC) [2] is the most popular technique in the serial input and serial output scenarios. Single path delay feedback (SDF) architecture is proposed to reduce the memory banks in the pipelines [3]. The SDF concept extended to radix 2 to radix 2 k [4][5][6]. The high throughput requirements of communication services encouraged to multipath delay commutators [7] and multipath delay feedback (MDF) [8].
The MDF structures are formed using multiple interconnected SDFs. The MDF scheme is utilized in various applications due to its efficient memory usage, but suffers from arithmetic resource utilization and it is rectified in M 2 DF architecture [9], which utilizes the folding transformation technique for the significant reduction of arithmetic resources. In this work, tunable M 2 DF architecture is proposed to further reduce the arithmetic operations in terms of number of LUTs and registers.

Construction of M 2 DF Architecture:-
Design of parallel radix-2 k FFT processor based on folding transformations to derive the folding matrices of DIF and DIT of SDF structures. The pipelined structure is rescheduled by incorporating DIF blocks into DIT blocks to form M 2 DF architecture from the SDF architecture. The M 2 DF mainly focus on horizontal processing in relevant to the hardware implantations and is shown in Fig.1 Corresponding Author:-G. Ganga bhavani. Address:-Pg scholar, dept. Of ece, shri vishnu engg. College for women, bhimavaram.  Conventionally two different structures are used. One is Type-I, In this adders are shared by means of streams and is shown in Fig. 2(a). Another type of arithmetic unit is Type -II, In this type adders and multipliers are reused to pick up the equipment effectiveness and is shown in Fig. 2(b).
Proposed M 2 DF Architecture using the tunable Arithmetic Unit:-In the modified M 2 DF architecture the conventional arithmetic units are modified using tunable arithmetic units, while maintaining the feedback structure of conventional architecture. Fig. 3 shows the tunable arithmetic unit. In this 4-stage pipelined technique is adopted. This unit consists of 6 butterfly units and 3 complex multipliers. Compared to type I and type II AUs the proposed AU having high throughput and consumes less area. Due to the tunable arithmetic unit, the inexact multiplier configurations have much higher sensitivities than the most of the inexact adder configurations and the pipelined technique is effectively utilized. Due to these advantages tunable arithmetic unit has a double impact on the quality of solutions.  Here data_in _a and data_in_b are inputs indicates the iteration loops and data_out is the required output. The corresponding RTL schematic of radix-2 two parallel 512 point FFT architecture is shown in Fig. 5.