18Feb 2017

ANALYTICAL MODELING OF COST EFFICIENT QUAD MATERIAL GATE ALL AROUND STACK ARCHITECTURE OF TUNNEL FET.

  • Assistant professor , Department Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Cheeryal (V), Keesara Mandal, Ranga Reddy Dist.-501301, Telangana.
  • IV BTECH, Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Cheeryal (V), Keesara Mandal, Ranga Reddy Dist.-501301, Telangana.
  • IV BTECH, Department Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Cheeryal (V), Keesara Mandal, Ranga Reddy Dist.-501301, Telangana..
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Increase in speed is achieved by shrinking the dimensions of MOSFET?s. But scaling of parameters leads to short channel effects which degrade the device performance. The predominating problems associated with SCE?s are change in threshold voltage, drain-induced barrier lowering (DIBL) and sub threshold leakage current. SCE?s causes degradation of sub threshold slope and increase in drain off-current. Among the different possible solutions, TFETs are chosen to be the potential candidate because of its immunity against the SCEs, low leakage current and CMOS compatible technology. In order to incorporate the advantages of Surrounding Gate (SG), Quad Material Gate (QMG), Gate Stack Architecture (GSA) and Tunnel Field Effect Transistor (TFET), novel device architecture has been proposed known as Quad Material Gate All around Stack Architecture - Tunnel Field Effect Transistor (QMGAASA- TFET). Materials used: Oxide1: TiO2 (Titanium dioxide) Oxide2: HfO2 (Hafnium dioxide) Oxide3: SiO2 (Silicon dioxide) Oxide4: ZrO2 (Zirconium dioxide) Metal1: Gold Metal2: Silver Metal3: Aluminum Metal4: Copper

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    2. J Tanaka, T Toyabe, S Ihara, S Kimura, H Noda, and K Itoh. ?Simulation of sub-0.1-μm MOSFET?s with completely suppressed short-channel effect? IEEE Electron Device Letters, Vol. 14, No. 8, pp. 396?399, 1993.
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[G. Poshamallu, G. Siri Chandana and S. Sai Abhinav. (2017); ANALYTICAL MODELING OF COST EFFICIENT QUAD MATERIAL GATE ALL AROUND STACK ARCHITECTURE OF TUNNEL FET. Int. J. of Adv. Res. 5 (Feb). 774-782] (ISSN 2320-5407). www.journalijar.com

G.POSHAMALLU

DOI:

Article DOI: 10.21474/IJAR01/3213      
DOI URL: http://dx.doi.org/10.21474/IJAR01/3213

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