DESIGN OF HIGH SPEED,6-BIT PIPELINE ADC WITH BUILT-IN DIGITAL ERROR CORRECTION UNIT USING SUBMICRON CMOS TECHNOLOGY.

Manjuvani.K.M; Manasa k chigateri; Manjunath K M and  Sharan basavaraj B.

doi:10.21474/IJAR01/792

30 Jun 2016 Vol. 4 (06) pp. 519-524 DOI: 10.21474/IJAR01/792

DESIGN OF HIGH SPEED,6-BIT PIPELINE ADC WITH BUILT-IN DIGITAL ERROR CORRECTION UNIT USING SUBMICRON CMOS TECHNOLOGY.

Manjuvani.K.M, Manasa k chigateri, Manjunath K M and Sharan basavaraj B.

Assistant professor, Department of ECE, RYMEC, Bellary, Karnataka, India.

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Abstract

The paper describes a 6bit, 1Msps Pipeline Analog to Digital Converter implemented in 0.6?m CMOS technology. The design operates at ±5V dc supply. Circuit techniques used include a precise comparator, operational amplifier which works on 1.5bits per stage and non-overlapping clock. A switched capacitor is used to sample and multiply at each stage.

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How to Cite This Article

Manjuvani.K.M, Manasa k chigateri, Manjunath K M and Sharan basavaraj B. (2016); DESIGN OF HIGH SPEED,6-BIT PIPELINE ADC WITH BUILT-IN DIGITAL ERROR CORRECTION UNIT USING SUBMICRON CMOS TECHNOLOGY., Int. J. of Adv. Res., 4 (06), 519-524, ISSN 2320-5407. DOI: https://doi.org/10.21474/IJAR01/792

Corresponding Author

K M Manjuvani

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