SYNTHESIS AND FPGA VALIDATION OF PARALLEL PREFIX ADDERS
- M Tech Student, Dept. of Electronics and Communication Engineering,R. V. College Of Engineering, Bengaluru.
- Associate Professor, Dept. of Electronics and Communication Engineering, R. V. College Of Engineering, Bengaluru.
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In this work, the design implementation, functionality testing, design synthesis and bitstream generation of various n-bit adder architecture of RCA, CLA, CSkA and KSA. And addresses various forms of adders which include Ripple-carry (RCA), Carry-lookahead (CLA), Carry-skip (CSkA), and Kogge-stone (KSA) adders. Certain design restrictions for digital VLSI circuits, such speed and area, can be satisfied using these adders. All the mentioned adder are designed using Verilog HDL, implemented the same on Xilinx Vivado 2018.2, functionality test is carried out by writing testbench, bitstream generated for the same and synthesized using Cadence genus.
[Sandeep S. and Kiran V. (2022); SYNTHESIS AND FPGA VALIDATION OF PARALLEL PREFIX ADDERS Int. J. of Adv. Res. 10 (Oct). 708-717] (ISSN 2320-5407). www.journalijar.com
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