Realization of Data Encoding and Decoding Scheme for NOC Application

Network-on-chip (NoC) topology is composed by an arbitrary number of instances of three basic kind of functional blocks Network Interfaces, Links and Switches. In NoC the major source for power dissipation is the NoC links. The self and coupling switching activities are responsible for link power dissipation. In this paper we present a set of data encoding and decoding schemes operating at ?it level and on an end-to-end basis, which allows us to minimize both self and coupling switching activities. The self-switching is reduce by checking the switching transition and then the coupling technique is incorporated with the wormhole routed network, that is flits are encoded by the network interface before they are injected in the network and are decoded by the destination NI (network interface). Especially the decoding schemes are focused on reducing hardware. This paper analyzes the power and delay reduction of both encoding and decoding schemes and also analyzes the 3-bit odd and even inversion transition types in Xilinx Virtex-5 family (XC5VLX50)