An efficient approach for Boundary Scan Verification for a System-on-Chip

System-on-Chip is an Integrated Circuit(IC) that integrates different modules on a single chip. It consists of different Intellectual Properties (IP’s) from different vendors. Verifying such a complex IC is challenging as it consists of analog, digital and glue logic on a single chip. As a part of pre-silicon verification, Boundary-scan involves checking interconnection between different components. Due to integration of different IP’s with forming heterogeneous pin structure at SOC level, boundary-scan cells incorporated per pin will also vary according to the pin structure. Some pins are single ended and others may be differential, some are slow speed pins and some pins allow high-speed data transaction. Boundary-scan verification infrastructure needs to be updated for different projects, as it involves updating the pins present at SOC level. In this project, an approach is proposed to verify boundary-scan logic for an SOC. Automated script is developed to automatically update the changes required. This helps in reducing time spent in updating the changes, which would require a manual intervention of couple of weeks.