Time Efficient Implementations of Matrix Multiplication.

Matrix multiplication is use in various areas of engineering field such as digital signal and image processing, microprocessor and microcontroller base design etc. In digital signal processing circular convolution of two signals in discrete fourier transform is done through matrix method. The Filter design in DSP requires efficient multiplication and accumulation operations are perform using matrix method. In this work a processing element is design which includes the small sub modules of adder, counters, multipliers, matrix arrangement block, SRAM and FIFO etc. The work on paper is base on VHDL (Very High Speed Integrated Circuit Hardware Description Language) implementation of well-organized design of parallel matrix multiplication with reduce gate counts. The computational time, latency and throughput is improved. The results are simulated to demonstrate the accuracy and matrix size capacity of the architecture. The design is done on the basis of blocking and parallelization. Blocked matrix multiplication enables processing randomly large matrices using partial memory capability, and decrease the bandwidth requires across the device boundaries by recycle the existing elements. The propose algorithm verify low execution times while limiting the gate count.