Vol. 5 (03) pp. 795-807 DOI: 10.21474/IJAR01/3574

AN EFFICIENT DESIGN OF DIGITAL DOWN CONVERTER FOR SOFTWARE DEFINED RADIO APPLICATION

, and
  • M.tech, VLSI and Embedded system, Department of ECE, Hindustan Institute of Technology and Science, Chennai.
  • Assistant Professor (S.G), Department of ECE, Hindustan Institute of Technology and Science, Chennai.
71 Downloads 198 Views
Crossref

Download Full Paper (PDF)

Abstract

Adaptive wave pipelining is the methodology used for improving the overall performance of Software Defined Radio (SDR). This method is a functional combination of wave pipelining and hybrid technique. Wave pipelining is the methodology used for improving the performance without using the intermediate latches, at the same time it performs the same operation as pipelining. Hybrid technique is the mechanism that is used for introducing registers for achieving the timing constrain. This technique is implemented in the Direct Digital Synthesizer (DDS) which is the integral part of a Digital Down Converter (DDC) in the Digital Front End (DFE)/ Intermediate Frequency (IF) of Software Defined Radio (SDR). This paper presents the principles of wave pipelining and the method for executing the computer algorithm named Coordinate Digital Rotation Digital Computer (CORDIC) using wave pipelining. Xilinx ISE 14.75 design suite is used as the software for simulation of the proposed system.

Keywords

Article Analytics

References

  1. M.Lalge, M.S.Karpe , S.U.Bhandari, “Software Defined Radio Principles and Platforms”. International Journal of Advanced Computer Research (ISSN (print): 2249-7277 ISSN (online): 2277-7970) Volume-3 Number-3 Issue-11 September-2013.
  2. Godbole B. B, Nikam R.H., Pandit M.D, “A Review of Cordic Algorithm in DDS Based Communication Systems”. International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 2, February 2014).
  3. Sandhya, Syed Inthiyaz, Dr. Fazal Noor Basha, “Power and Area Optimization for Pipelined CORDIC Processor Architecture in VLSI”. International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 3, May-Jun 2012, pp.1588-1595.
  4. Lattice semiconductor cooperation, “Digital Up/Down Converter (DDC/DUC) for WiMAX Systems.” May 2008 Reference Design RD1036.
  5. Chestnut Court, Burton Row, Brent Knoll, Somerset, TA9 4BP, UK “The Theory of Digital Down Conversion”. Rev 1.2 T.Hollis/R.Weir 26-06-2003
  6. S.Sushmitha, G.Vimala Kumari, Department of ECE, MVGR COLLEGE OF ENGINEERING Vizianagaram, A.P, INDIA, “Design and Implementation of Wideband Digital Down Converter on FPGA”. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology Volume 1, Issue 4, June 2012.
  7. Uday Kumar. K, K. Bapayya, Sandeep. M, “FPGA Implementation of Digital Down Converter using Multiplier-Free Filter”. International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 www.ijert.org IJERTV3IS100560 (This work is licensed under a Creative Commons Attribution 4.0 International License.) Vol. 3 Issue 10, October- 2014.
  8. Menakadevi, M.Madheswaran, “Direct Digital Synthesizer using Pipelined CORDIC Algorithm for Software Defined Radio”. Volume 2 No.6, June 2012 ISSN 2224-3577 International Journal of Science and Technology ©2012 IJST. All rights reserved.
  9. McEwan and S. Collins, “Direct Digital- Frequency Synthesis by Analog Interpolation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1294 – 1298, Nov. 2006.
  10. International Journal of Advanced Computer Research (ISSN (print): 2249-7277 ISSN (online): 2277-7970) Volume-3 Number-3 Issue-11 September-2013 133 “Software Defined Radio Principles and Platforms” A.M.Lalge, M.S.Karpe , S.U.Bhandari.
  11. Lakshmi and A. S. Dhar, “CORDIC Architectures: A Survey,” VLSI Design, vol. 2010, pp. 1- 19, 2010.
  12. Maher Jridi, “Direct Digital Frequency Synthesizer with CORDIC Algorithm and Taylor Series Approximation for Digital Receivers” European Journal of Scientific Research ISSN 1450-216X Vol.30 No.4 (2009), pp.542-553.
  13. Shruti S.Desai, Prof. A.S.Joshi, “DDS architecture for digital frequency Generation” International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 1, January 2013.
  14. Cordesses, “Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 2),” IEEE Signal Processing Magazine, vol. 21, no. 5, pp. 110 – 112, Sept. 2004.
  15. Wayne P. Burleson, Member, IEEE, Maciej Ciesielski, Senior Member IEEE, Fabian Klass, Associate Member IEEE, and Wentai Liu, Senior Member IEEE,” Wave-Pipelining: A Tutorial and Research Survey”. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998.
  16. K. C. Lam, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Valid clocking in wavepipelined circuits,” in Proc. Int. Conf. Computer-Aided Design, 1992.
  17. Wong, G. De Micheli, and M. Flynn, “Inserting active delay elements to achieve wave pipelining,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1989, pp. 270–273.
  18. P. Burleson and W. Liu, \Wave-pipelining: a tutorial and research survey", IEEE Trans. on VLSI Systems, Vol.6, No.3, pp.464 {474, 1998}.

How to Cite This Article

Parameshwar. S, M. Rajmohan and Punithavathy Mohan. (2017); AN EFFICIENT DESIGN OF DIGITAL DOWN CONVERTER FOR SOFTWARE DEFINED RADIO APPLICATION, Int. J. of Adv. Res., 5 (03), 795-807, ISSN 2320-5407. DOI: https://doi.org/10.21474/IJAR01/3574

Corresponding Author

PARAMESHWAR. S
STUDENT
Creative Commons Attribution 4.0 This work is licensed under a Creative Commons Attribution 4.0 International License.