TUNABLE MIXED DECIMATION MULTIPATH DELAY FEEDBACK FOR RADIX 2K FFT
- PG scholar, Dept. of ECE, Shri Vishnu Engg. College for women, Bhimavaram.
- Professor & Head, Dept. of ECE, Shri Vishnu Engg. College for women, Bhimavaram.
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The Decimation Multipath Delay Feedback (M2DF) is a technique for the radix 2k FFT, which eliminates the stand by time of arithmetic modules in computing units. In this paper tunable M2DF architecture is proposed. In this, tunable arithmetic units are utilized in place of conventional arithmetic units to overcome the under utilization of arithmetic units in conventional M2DF architecture. The results show that, the tunable M2DF technique utilizes the lesser number of LUTs and slice registers than the conventional M2DF technique. In addition, the proposed technique having advantage of high throughput with reduced delay and area compared with conventional M2DF.
- Garrido, J. Grajal, M. A. Sanchez, and O. Gustafsson, ?Pipelined radix-2k feed forward FFT architectures,? IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 21, no. 1, pp. 23?32, Jan. 2013.
- Jian Wang, ChunlinXiong, Kangli Zhang, and Jibo Wei, ?A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT? IEEE transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, january 2016.
- Cortes, I. Velez, and J. F. Sevillano, ?Radix rk FFTs: Matrical representation and SDC/SDF pipeline implementation,? IEEE Trans. Signal Process., vol. 57, no. 7, pp. 2824?2839, Jul. 2009.
- He and M. Torkelson, ?Design and implementation of a 1024-pointpipeline FFT processor,? in Proc. IEEE Custom Integr. Circuits Conf., May 1998, pp. 131?134.
- Ayinala, M. Brown, and K. K. Parhi, ?Pipelined parallel FFT architectures via folding transformation,? IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 6, pp. 1068?1081, Jun. 2012.
- K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. Hoboken, NJ, USA: Wiley, 1999.
- Li and N. P. Van Der Meijs, ?A radix-22 based parallel pipeline FFT processor for MB-OFDM UWB system,? in Proc. IEEE Int. SOC Conf., Sep. 2009, pp. 383?386.
- -N. Tang, J.-W. Tsai, and Z. Wang, X. Liu, B. He, and F. Yu.:A combined SDC-SDF architecture for normal?? I/O pipelined radix-2 FFT.IEEE Trans.? Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 5,? pp. 973?977, May 2015.
- N. Tang, C.H.Liao, and T.-Y. Chang, ?An area- and energy-efficient multimode FFT processor for WPAN/WLAN/WMAN systems,? IEEEJ. Solid-State Circuits, vol. 47, no. 6, pp. 1419?1435, Jun. 2012.
- H. Wold and A. M. Despain, ?Pipeline and parallel-pipeline FFT processors for VLSI implementations,? IEEE Trans. Comput.,vol. C-33, no. 5, pp. 414?426, May 1984.
- E. Volder, "The CORDIC trigonometric computing technique," IRE Trans. Electron. Comput., vol. EC-8, pp. 330-334, Sept. 1959.
- -J. Yang, S.H.Tsai, and G. C. H. Huang, ?MDC FFT/IFFT processor with variable length for MIMO-OFDM systems,? IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 4, pp. 720?731, Apr. 2013.
[G. Ganga Bhavani and G. R. L. V. N Srinivasa Raju. (2018); TUNABLE MIXED DECIMATION MULTIPATH DELAY FEEDBACK FOR RADIX 2K FFT Int. J. of Adv. Res. 6 (May). 644-650] (ISSN 2320-5407). www.journalijar.com
PG SCHOLAR, DEPT. OF ECE, SHRI VISHNU ENGG. COLLEGE FOR WOMEN, BHIMAVARAM