AN EFFICIENT LOW POWER DESIGN OF SAR BASED ADC USING DEEP SUBMICRON 45 NM CMOS TECHNOLOGY
- Research Scholar, VLSI, Department of Electronics & Telecommunication Engineering, Bapurao Deshmukh College of Engineering, Sewagram, Wardha (M.S.).
- Assistant Professor, Dr.Girish D. Korde, Department of Electronics & Telecommunication, Bapurao Deshmukh College of Engineering, Sewagram, Wardha (M.S.).
- Assistant Professor, Anant W. Hinganikar, Department of Electronics & Telecommunication, Bapurao Deshmukh College of Engineering, Sewagram, Wardha (M.S).
- Abstract
- Keywords
- Cite This Article as
- Corresponding Author
A 4-bit Successive Approximation Register (SAR) logic based Analog to Digital Converter (ADC) is designed using Up-down counter as SAR logic for low power operation. The advancement in CMOS technology is going on day by day. With this advancement, more & more signal processing functions are incorporated in the digital field for low cost, low power consumption and dissipation. The designed CMOS based ADC structures provide optimum results for all three circuit design challenges as speed, area and power. Among various ADC topologies, we opted to implement up-down counter based Successive Approximation Register (SAR) ADC that is one of the best suited for low power. We target a resolution of 4-bit and a power consumption of few mill watts. The SAR ADC is implemented in 45nm CMOS technology with a power supply of 1V.
[Monu Raju Thool, Dr. Girish D. Korde and Prof. Anant W. Hinganikar (2022); AN EFFICIENT LOW POWER DESIGN OF SAR BASED ADC USING DEEP SUBMICRON 45 NM CMOS TECHNOLOGY Int. J. of Adv. Res. 10 (May). 109-117] (ISSN 2320-5407). www.journalijar.com
Research Scholar, VLSI, Department of Electronics & Telecommunication Engineering, Bapurao Deshmukh College of Engineering, Sewagram, Wardha (M.S.).
