SUSTAINABLE IOT HARDWARE DESIGN USING AI-BASED VLSI POWER OPTIMIZATION TECHNIQUES

The rapid growth of Artificial Intelligence (AI) and Internet of Things (IoT) has intensified the demand for energy-efficient, high-performance hardware capable of real-time processing at the network edge. Conventional Very Large Scale Integration (VLSI) design methodologies are increasingly inadequate for meeting simultaneous constraints of power efficiency, performance, and sustainability. This paper presents an AI-Optimized VLSI architecture that integrates machine learning-based design-space exploration with adaptive power management techniques to achieve improved energy efficiency for IoT systems. The proposed framework leverages Reinforcement Learning (RL), Genetic Algorithms (GA), and Bayesian Optimization (BO) to optimize power-performance-area (PPA) trade-offs during synthesis and layout stages. In addition, dynamic voltage and frequency scaling (DVFS), clock gating, and power gating techniques are incorporated to minimize dynamic and leakage power consumption. Simulation results using Cadence Innovus and Synopsys Design Compiler demonstrate a 43.3% reduction in power consumption, 29.7% reduction in delay, and 52% improvement in energy efficiency compared to conventional VLSI architectures. The results confirm that AI-driven hardware optimization significantly enhances the sustainability and scalability of IoT edge systems.