Asynchronous Data Sampling in Double Edge Triggered Flip-flops with Clock Gating

For synchronous designs, a large portion of the total power consumption of integrated circuits is mainly due to the storage elements and clock distribution. Normally storage element will be flip-flops. In low power circuit design, clock elements play an important role in energy efficiency. One technique to reduce power consumption is to use double edge triggered flip-flops which provides the same throughput as the single edge triggered flip-flop while only using half of the clock frequency. Another technique to reduce power consumption is clock gating. However incorporating clock gating with double edge triggered flip-flops to further reduce power consumption introduces asynchronous data sampling which means that the output changes between the clock edges. Along with asynchronous data sampling, a method to avoid the same is designed. These circuits are designed in 180nm CMOS technology and simulated using Cadence Virtuoso software.