TSPC Based State Look Ahead Counter

The speed of the circuit is one of the important performance factors, which determines the overall efficiency of the circuit. The selection of best counter topology is essential since counters are the basic building blocks of memory select management, code generators, shifters, frequency dividers and various arithmetic operations. TSPC based state look ahead counter is the best counter architecture when considering area, power consumption, speed, skew and operating frequency. This counter topology has two paths: - State look ahead path and Counting path. Both these path uses True single Phase (TSPC) D Flip-flop which is the main attraction of the entire Counter Architecture .This structure uses only three blocks in a repeated fashion so the design time of the counter is reduced compared to conventional synchronous counter. The proposed counter is designed in 180nm CMOS technology and simulated using Cadence Virtuoso software.