DESIGN AND STUDY OF A 20 NANOMETER NANOSHEET FIELD EFFECT TRANSISTOR AND EVALUATE ITS PERFORMANCE

The continued downscaling of semiconductor devices to overcome the limitations of traditional FinFETs and mitigate short-channel effects (SCEs) necessitates the adoption of novel device architectures. The gate-all-around (GAA) nanosheet field-effect transistor (NSFET) has emerged as a promising candidate for sub-7-nm and beyond technology nodes due to its superior electrostatic control and improved current drive capability. This research presents a comprehensive modeling and performance evaluation of a 20 nm gate length (Lg) silicon-based NSFET using three-dimensional (3D) technology computer-aided design (TCAD) simulations. The study systematically investigates the influence of key geometrical parameters, such as nanosheet width (Wns) and thickness (Tns), on critical direct-current (DC) performance metrics, including: Ion, Ioff, SS, DIBL. The simulation results demonstrate that the 20 nm NSFET exhibits excellent performance DC characteristics, and a steep subthreshold swing, making it highly suitable for low-power and high-speed switching applications.