AES ALGORITHM IMPLEMENTATION FOR SECURE DATA AND IMAGE TRANSMISSION USING VERILOG

Data and image security are critical concerns in modern digital communication. The Advanced Encryption Stan- dard (AES) is widely used for secure data transmission due to its robustness and efficiency. This paper presents an FPGA-based implementation of AES encryption and decryption using Verilog for secure data and image transmission. The proposed design is implemented on a Xilinx FPGA platform to ensure high- speed encryption with minimal hardware resource utilization. The AES algorithm is optimized using pipeline architecture to enhance performance, supporting 128-bit encryption and decryption. Experimental results demonstrate the systems ability to encrypt and decrypt both textual and image data efficiently. Power consumption, resource utilization, and timing performance are analyzed, showing that FPGA-based AES provides a secure and efficient solution for real-time data protection in embedded systems. The proposed approach is suitable for applications in secure communication, cloud storage, and military-grade encryption.