DESIGN AND IMPLEMENTATION OF A HIGH-SPEED 32-BIT SIGNED VEDIC MULTIPLIER USING CARRY LOOKAHEAD ADDERS

This paper presents the design and implementation of a high-speed 32-bit signed Vedic multiplier based on the Urdhva Tiryakbhyam sutra of Vedic mathematics, utilizing Verilog HDL and fast Carry Lookahead Adders. The proposed architecture recursively combines smaller signed Vedic multipli- ers and efficient adder modules to achieve parallel generation of partial products and rapid accumulation, significantly improving computational speed over conventional multiplication techniques. The multiplier supports both signed and unsigned operations, implementing robust logic for sign handling via twos complement conversion and Ex OR based sign determination. Simulation and verification are conducted using Xilinx Vivado, demonstrating correctness and performance suitable for applications in digital signal processing, arithmetic logic units, and custom VLSI-blocks. The results highlight the advantages of Vedic mathematical prin- ciples in modern digital hardware, offering improved throughput and efficiency for high-performance arithmetic operations.