HIGH-PERFORMANCE DADDA MULTIPLIERS FOR FPGA-BASED HARDWARE ACCELERATORS

Multiplication plays a crucial role in arithmetic circuits, digital signal processing,and machine learning accel- erators, where power efficiency and computational performance are key concerns. The Dadda multiplier is widely used due to its optimized reduction process, making it a popular choice for high-speed applications. However, conventional multipliers require substantial power and hardware resources, making them less suitable for low-power applications. This paper proposes a power-efficient Dadda multiplier that integrates an Approximate 4:2 Compressor to minimize power consumption and hardware complexity while maintaining an acceptable level of accuracy. The design is implemented using Verilog HDL and synthesized on an FPGA to evaluate its performance. The impact of approximation on delay, power, and area trade-offs is examined, showing notable reductions in power dissipation and hardware overhead compared to traditional Dadda multipliers. Experimental results demonstrate that the proposed approximate Dadda multiplier achieves lower power consumption with minimal accuracy loss, making it well suited for error resilient applications such as image processing, neural networks, and edge computing. This work highlights the advantages of approximate computing in arithmetic circuit design, contributing to the development of more energy-efficient hardware architectures.